? semiconductor components industries, llc, 2007 august, 2007 - rev. 3 1 publication order number: NB3N2304NZ/d NB3N2304NZ 3.3v 1:4 clock fanout buffer description the NB3N2304NZ is a low skew 1-to 4 clock fanout buffer, designed for high speed clock distribution such as in pci-x applications. the NB3N2304NZ guarantees low output-to-output skew. optimal design, layout and processing minimizes skew within a device and from device-to-device. the output enable (oe) pin forces the outputs low when low. features ? input/output clock frequency up to 140 mhz ? low skew outputs (100 ps) ? output enable ? operating range: v dd = 3.0 v to 3.6 v ? ideal for pci-x and networking clocks ? packaged in 8-pin tssop, 4.4 mm x 3 mm ? industrial temperature range ? these are pb-free devices* *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. tssop-8 dt suffix case 948s marking diagram* http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information figure 1. simplified logic diagram 40n yww a a = assembly location y = year ww = work week m = date code = pb-free package dfn8 mn suffix case 506aa 6o m 14 1
NB3N2304NZ http://onsemi.com 2 figure 2. block diagram figure 3. NB3N2304NZ package pinout (top view) q1 q2 q3 q4 in logic control oe 1 2 3 4 8 7 6 5 q4 q3 v dd q2 in oe q1 gnd table 1. pin description pin # pin name type description 1 in lvcmos/lvttl input clock input 2 oe lvcmos/lvttl input output enable for the clock outputs. outputs are enabled when forced high. outputs are forced to logic low when oe is forced low. 3 q1 lvcmos/lvttl output clock output 1 4 gnd power negative supply voltage; connect to ground, 0 v 5 q2 (lv)cmos/(lv)ttl input clock output 2 6 v dd power positive supply voltage (3.0 v to 3.6 v) 7 q3 (lv)cmos/(lv)ttl output clock output 3 8 q4 (lv)cmos/(lv)ttl input clock output 4 ep (dfn8) exposed pad must be connected to a sufficient thermal conduit. electrically connect to the most negative supply or leave floating open. table 2. oe, output enable function table inputs outputs in oe l l l h l l l h l h h h
NB3N2304NZ http://onsemi.com 3 table 3. attributes characteristics value esd protection human body model machine model > 2kv > 200 v moisture sensitivity, indefinite time out of drypack (note 1) tssop-8 dfn-8 level 3 level 1 flammability rating oxygen index: 28 to 34 ul 94 v-o @ 0.125 in transistor count 480 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v dd positive power supply gnd = 0 v v dd + 0.5v v v i input voltage gnd C 0.5 v i v dd + 0.5 v t a operating temperature range, industrial -40 to +85 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) 0 lfpm 500 lfpm 0 lfpm 500 lfpm tssop-8 tssop-8 dfn-8 dfn-8 143 103 129 84 c/w t sol wave solder pb-free (note 2) 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. edec standard multilayer board - 2s2p (2 signal, 2 power).
NB3N2304NZ http://onsemi.com 4 table 5. dc characteristics v dd = 3.0 v to 3.6 v, gnd = 0 v, t a = -40 c to +85 c symbol characteristic min typ max unit i dd power supply current @ 66.66 mhz, unloaded outputs 12 25 ma v oh output high voltage - ioh = -24 ma -ioh = -12 ma 2.0 2.4 v v ol output low voltage -iol = 24 ma -iol = 12 ma 0.8 0.55 v v ih input high voltage, in and oe (note 3) 2.0 v v il input low voltage, in and oe (note 3) 0.8 v i ih input high current, v in = v dd -50 50 a i il input low current, v in = 0 v -100 100 a cin input capacitance, in, oe 5 7 pf note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. in input has a threshold voltage of v dd /2. table 6. ac characteristics v dd = 3.0 v to 3.6 v, gnd = 0 v, t a = -40 c to +85 c (note 4) (figure 4) symbol characteristic min typ max unit f in input clock frequency dc 140 mhz t dcskew duty cycle skew = t2 t1 (figure 4) measured at 1.5 v 40 50 60 % tr/tf output rise and fall times; 0.8 v to 2.0 v 0.9 1.5 ns t pd propagation delay, in-to-qn (note 5) 2.5 3.5 5 ns t skew output-to-output skew; (note 5) 100 ps t pu powerup time for v dd to reach minimum specified voltage 0.05 50 ms note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. all outputs loaded equally with c l = 25 pf to gnd. duty cycle out = duty in. a 0.01 f decoupling capacitor should be connected between v dd and gnd. 5. measured on rising edges at v dd 2; all outputs with equal loading.
NB3N2304NZ http://onsemi.com 5 figure 4. switching waveforms duty cycle timing all outputs rise/fall time output-output skew input-output propagation delay 1.5 v 1.5 v 2.0 v 0.8 v 0.8 v 2.0 v 1.5 v 1.5 v 1.5 v 3.3 v 0 v output output input output output t 1 t 2 t r t f t skew v dd /2 v dd /2 t pd ordering information device package shipping ? NB3N2304NZdtg tssop-8 (pb-free) 100 units / rail NB3N2304NZdtr2g tssop-8 (pb-free) 2500 / tape & reel NB3N2304NZmnr4g* dfn8 (pb-free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *contact a sales representative.
NB3N2304NZ http://onsemi.com 6 package dimensions tssop-8 case 948s-01 issue b dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 4.30 4.50 0.169 0.177 c --- 1.10 --- 0.043 d 0.05 0.15 0.002 0.006 f 0.50 0.70 0.020 0.028 g 0.65 bsc 0.026 bsc l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-. seating plane pin 1 1 4 85 detail e b c d a g l 2x l/2 -u- s u 0.20 (0.008) t s u m 0.10 (0.004) v s t 0.076 (0.003) -t- -v- -w- 8x ref k ident k 0.19 0.30 0.007 0.012 s u 0.20 (0.008) t p1 p detail e f m 0.25 (0.010) ??? ??? k1 k jj1 section n-n j 0.09 0.20 0.004 0.008 k1 0.19 0.25 0.007 0.010 j1 0.09 0.16 0.004 0.006 p --- 2.20 --- 0.087 p1 --- 3.20 --- 0.126 n n
NB3N2304NZ http://onsemi.com 7 package dimensions dfn8 case 506aa-01 issue d notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 . 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. ???? ???? ???? ???? a d e b c 0.10 pin one 2 x reference 2 x top view side view bottom view a l (a3) d2 e2 c c 0.10 c 0.10 c 0.08 8 x a1 seating plane e/2 e 8 x k note 3 b 8 x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 2.00 bsc d2 1.10 1.30 e 2.00 bsc e2 0.70 0.90 e 0.50 bsc k 0.20 --- l 0.25 0.35 1 4 8 5 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 NB3N2304NZ/d literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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